Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.
There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...
TetraMAX II ATPG reduced test generation runtime by an order of magnitude, from an overnight run to less than one hour, while producing 50 percent fewer patterns DecaWave met their silicon test time ...
Moore’s law has been the standard reference for semiconductor scaling. It roughly says that semiconductor design sizes, fueled by technology improvements, double every two years. Consequentially, the ...
With every process node advance, new types of manufacturing defects manifest. These defects are especially prevalent during the early phase. For early adopters, silicon manufacturing tests must evolve ...
Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a ...
The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results