Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

WILSONVILLE, Ore., May 18, 2015 -- Mentor Graphics Corp. (NASDAQ: MENT) today announced that Mellanox Technologies has standardized on the new Mentor® Tessent® Hierarchical ATPG solution to manage the ...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

Moore’s law has been the standard reference for semiconductor scaling. It roughly says that semiconductor design sizes, fueled by technology improvements, double every two years. Consequentially, the ...

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...

This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines ...

The ability to create and choose the most effective test patterns has become more daunting as more patterns are introduced, says Ron Press of Siemens Digital Industries. Choosing the most efficient ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...